Re: PCI Streaming Bit...

[Bob Sugar <bobs@fusionmm.com>]

Dimitry,

About a year ago, after having similar PCI performance problems,
Graeme Gill of this newsgroup told me about the "Snoop Ahead
Disable" bit in the Intel 430HX (Triton II) and 430VX (Triton
III) Chipsets  (0x50 bit 1).  This bit allows PCI bursting to
continue across cache line boundaries by pre-snooping the next
cache line address.  When the next PCI transfer comes, the
chipset has already done the snoop and cache flush (if needed).
Without snoop ahead, the chipset needs to disconnect at the
beginning of each cache line while it performs the snoop and flush.

Intel apparently had some bugs in some versions of the Triton II
(HX) and Triton III (VX) chipsets that could be patched around
by disabling snoop ahead.  Some BIOSes always disable snoop ahead
on all Triton chips even though the problem has been fixed in
newer chips.  A year ago, the description for this bit could only
be found in the Errata for the HX and VX chipsets.  I don't know
where it's documented today.  The old Intel errata said:

  "Disabling Snoop Ahead affects PCI-to-memory bandwidth, there
   is no performance impact to commonly run benchmarks or desk
   top applications."

PCI has apparently come a long way in the last couple years...


Here's my old benchmark numbers from running burst transfers on an i960RD
development board with snoop ahead disabled and enabled.

  RD PCI Performance with Snoop Ahead disabled:
  10000 4096-byte block reads  (10 blks/chain):  2.9 clks/word  45.9 MB/sec
  10000 4096-byte block writes (10 blks/chain):  2.2 clks/word  61.9 MB/sec

  RD PCI Performance with Snoop Ahead enabled:
  10000 4096-byte block reads  (10 blks/chain):  1.5 clks/word  87.4 MB/sec
  10000 4096-byte block writes (10 blks/chain):  1.3 clks/word 104.8 MB/sec


Sincerely,


Bob Sugar
Senior Systems Engineer
Fusion MicroMedia Inc.


At 02:55 PM 4/24/98 -0400, Dimitry Korsunsky wrote:
>	Greetings and Salutations,
>
>	This is a question regarding the performance of a DMA initiated
>by a PCI bus master to the host.
>
>	We have a situation where for some reason DMA is exhibiting
>extremely poor performance (i.e. something 	around 30 MB/s).  We
>have been researching this issue and have found multiple references to
>an elusive bit
>	in the Intel chipsets called the "PCI Streaming Bit".  The
>original message we were looking at was posted by 
>	one Gary Stein.  Now, what we are seeing is very similar to what
>Mr. Stein describes, i.e. DMA gets 	disconnected by the host after
>transferring 8 DWORDs.  However, we have not been able to find any
>documentation or reference to that PCI Streaming bit anywhere.  
>
>	If anybody has any experience with PCI Burst performance issues,
>your words of wisdom would be 	extremely helpful.  Also, if anybody
>knows anything about this PCI Streaming bit that information would be
>invaluable to us (my guess is, Mr. Stein, for one, knows a lot).  
>
>	Thanks you in advance.
>
>	Dimitry Korsunsky
>	ICE