Big/Little Endian issues

[anagaraj@assuredaccess.com (Ashwath Nagaraj)]

In a 32-bit system. if the communication between a little-endian host CPU
and a big-endian controller CPU (i.e. memory to memory transfer) is such
that :

1. all the elements in a data-struct passed from one to the other are aligned 
   to respective boundaries (i.e. 'long's to 32-bit boundary, 'short's to 
   16-bit boundaries, (and, of course, 'char's to 8-bit boundaries), AND

2. The host and controller can ensure that the alignment of theirs structures 
   in their respective memories, AND

3. the size of the transfer is a multiple of 32-bits, AND

4. the bus hardware does a 32-bit byte-lane swap, AND 

5. the destination-CPU makes corresponding changes in the struct definition
   w.r.t. the source, 

then the requirement of software swapping for this data-structure is
eliminated.

In the perspective of a company where code for both the driver (running on
the host-CPU) and an intelligent-controller are written, it would be great
to have the hardware do the swap.

Been there and done that too.. however, the only way we could figure out
the actual data path was to transfer a known pattern, and see what arrived
!! (Various combinations of swaps for a misaligned transfer result in the
head or tail  being missing.)

Wearing a hardware designer hat - the hardware can only "know" the
alignment of bytes, so I would provide a mechanism to transfer byte string
from a source memory to a destination memory. This may involve byte-lane
swaps.

All this about byte-endianness..

Next subject - bit-endianness a la big-blue....

Ashwath Nagaraj