[Re: target termination]

[Michael Tresidder <tresidd@vcubed.com>]

Hello again,

Judging from the emails I have recieved, it has become apparent
that there are a number of people that took my original email
(not included here due to length) the wrong way. Please let me
take this opportunity to "set-the-record-straight".

First, the devices produced by V3 *do not* exhibit the behaviour
of my Fig. 1. V3's devices operate in accordance with the
PCI 2.1 Spec.

Also, I was not asking whether the waveform in the first figure
violated the PCI Spec. Rev. 2.1. I was completely aware that it
did. By virtue of the fact that it violates the spec, the master's
behaviour under that case is undefined. In particular, some
devices/trackers may get lost (which I personally think is an
ungraceful way of handling the case), some devices may view
it as a transfer (graceful), and some may view it as a non-transfer
(also graceful). In any event, any of these interpretations is valid.

Additionally, I was not trying to ram this down anyones throat.
Basically, my thoughts were that if everyone handled the case
gracefully, and viewed it as a transfer, then PCI could be
expanded (with minimal grief) to incorporate the case and thus
shave a cycle.

Granted, the probability of everyone choosing to handle the case
by viewing it as a transfer is pretty minescule. However, the way I
see it is... It doesn't hurt to ask. Nothing ventured, nothing gained.

Also, some people point out that the performance improvements
would be minimal. To that I say, consider the cost. It's essentially
free. The cost of the interpretation I proposed is equavalent to any
other in terms of gate-count. So, if it were miraculously true that
everyone could handle the case as I described it, then why would
anyone resist it. When its free, why does it matter what minimal
performance improvement it might provide.

Alas, some of you who responded to my post indicated that your
devices did not deal with the erroneous case as I described.
Clearly then, this case *cannot* be sanctioned by the PCI spec.
That, in a nutshell, was all that I wanted to know. For those who
provided this feedback, I thank you for properly interpreting my
post. Your feedback was well received.

Regards,

Michael Tresidder
V3 Semiconductor