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Re: BE/LE
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: BE/LE
- From: "chefren" <chefren@pi.net>
- Date: Fri, 8 May 1998 17:39:29 +0200
- Comments: Authenticated sender is <hagens@pop.pi.net>
- In-reply-to: <199805071805.LAA10830@cherbourg.eng.efi.com>
- Posted-Date: Fri, 8 May 1998 17:37:40 +0200 (MET DST)
- Priority: normal
- Reply-to: chefren@pi.net
- Resent-Date: Sat, 9 May 1998 02:56:02 -0700
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On 7 May 98 at 11:05, Philip Ronzone wrote:
..
> Sorry that you didn't recognize the tongue-in-cheek paragraph.
O sorry, I didn't put in enough dots... ... ... ... After
sending I thought "it could come over too serious"...
> Intel had proposed somnething like this for a really cheap
> mostly-software modem -- to which I thought "what a great
> idea. For Intel. Dump a $9 part, and use 80% of the
> CPU cycles of a $350 part."
Well that was a little overblown at that time from Mr
Grove and I think it still is. Nowadays there are 2-4
times faster CPU's. Within 2 generations those old 80%
will be less than 10%. Since most people use a modem not
all the time it will be about 1-5% of a $350 part in the
near furture. (Hehe... I observe lots of people that use
40-80% of their CPU time for MP3 decoding and they have no
problems with the performance penalty!)
However... I bet a big part of the 80% you mentioned was
caused by the ISA bottleneck and maybe no busmastering
or DMA...
..
> > The trick is to get the data as fast as possible into the
> > CPU. Without letting the CPU wait for it or slowing it
> > down. So a good UART has a databus interface as wide as
> > the CPU databus and busmastering.
>
> The point is that getting the data into the CPU is only PART
> of the problem. If, after getting the data into the machine,
> the software has to, say, BE/LE swap, and align buffers etc.,
> the advantage of high speed device<->cpu data transfer is
> weakened.
Of course there is some weakening, I only try to state
that a 400MHz 32 or 64 bit CPU loses only one or two
400 MHz cycles to do a BE/LE swap or align buffers. That's
about 1/10 or less of one 33MHz PCI bus cycle.
A perfect design will always be faster but CPU's are so
incredible fast these days that functionality that was done
in hardware in the past can be done in software -cheaper-,
not faster(!).
If you can get a lower-cost BE than LE part and your design
is LE it might well be that less than 1% of the cycles of a
$350 CPU might compensate that. A price that halves every
18 months.
+++chefren
(Always a bit too serious?)
- References:
- BE/LE
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>