Re: Max retry ECR (fwd)

[Russ Herrell <russ@herrell.fc.hp.com>]

> 
> I don't quite see the problem.
> 
> The gfx controller can be designed to complete the frame buffer accesses
> (e.g. direct draw) bypassing the 2D/3D pipeline/engine. If arbitration at
> the frame buffer is done right, this will result in a maximum competion
> time well under 10us.

	Bypassing the entire 2D/3D pipeline does solve that problem.
	It creates a new flow control class, however, and now requires
	that extra buffering be added all the way up to the host interface
	block.  At no point between the host interface and the
	frame buffer's ram controller can the two flow control classes
	be mixed, else the 2D/3D pipeline will eventually
	hold off a Direct Draw access.

	If you want to accept burst writes to the Direct Draw space,
	you have to support some level of buffering in this flow control
	class.  

	On complex accelerators that are heavily pipelined, possibly
	through many chips, this extra, distinct flow control class can
	be a burden to support.  (And even if it is easy, it requires
	turning SEVERAL chips which is costly .. and offers no ROI to a lot of
	customers)	

	However, my real objection to the ECR is based more upon the 
	in-appropriateness of scope rather than the 
	implementation problems it poses.  
	The problem of isochronous behavior and real time response
	for a system cannot be solved by this change in the PCI spec alone.

	The proposed change does NOT deal with READS, which are much worse.
	The change does NOT deal with interrupt latencies.  The change
	does NOT deal with the interaction between AGP and PCI at the
	bus bridge.  I don't want to see us start to patch the PCI spec
	to solve half of a system level problem.  We can't possibly
	patch it enough.

	I could and do support a write timeout specified at the system
	level via PC-99.  It is really a system level response issue,
	and needs to be spec'ed at that level. 

	Besides, many systems, PC and RISC both, have no need to meet a 10 usec
	timeout on their PCI buses to be fully functional to their 
	intended market. Should we label those systems PCI non-compliant?


russ
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