Re: Capacitors on Power Pins

[Bob Mathews <bobm@lsil.com>]

Comments below,

Bob Mathews

William Benner wrote:

> Hello All,
>
> I have a few questions about the use of decoupling and bypass capacitors on
> the power pins of a PCI plug in board.
>
> I thought that I had read somewhere that each PCI plug in board must have
> capacitors on the power pins, even if these pins are not used by that
> particular board. But while examining other people's PCI boards, I don't see
> these. Am I mistaken or is this some minor violation of the spec?

Yes this seems to violate spec.  Most cards probably work most of the time
without them but for the most robust design all unused power of 5v, 3.3v and Vio
should be decoupled to ground to maxize the  AC return paths for your card.
You wouldn't leave off  half the ground pins just because you don't need them
for their DC current capacity would you?

>
>
> Another question, while designing my "Universal" 3V/5V board, I believe that
> the so called VIO pins will go unused by my design because I am using a 3.3V
> PCI chip that is 5V tolerant. I believe that the Gods that put together PCI
> did not anticipate such "5V tolerant but 3.3V powered" devices when they
> created the spec. Can I simply leave these VIO pins unconnected, or must I
> connect them and use a capacitor?

Are you really keying you card for universal application?  Just because the 3
volt powered chip can tolerate 5 v. inputs does not mean it may meet the spec.
in both a 5v and 3v system.  Does the manufacturer state that it meets spec in
both a 5v and 3v system?  The 3.3v section of the spec. essentially requires
high and low clamping diodes for cards that plug into 3 v connectors and these
clamp diodes must connect to 3.3 v in the 3 volt slot  and therefore they must
be connected to 5v in a 5 v connector other wise they would be forward biased in
the 5v system.

Does anyone else have any experience/comments on buffers in universal keyed
cards?


>
>
> Last question (for now), how exactly does this whole 3.3V powered devices
> which connect to the PCI bus "work" in a "reflected-wave switching"
> environment like PCI? According to PCI System Architecture book, "A
> carefully selected, relatively weak output driver is used to drive the
> signal line halfway to the desired logic state..." How does a 3.3V chip know
> what "halfway" is when it does not know if it is a 3.3V or 5V signaling
> environment? It must work because so far I have seen two PCI manufacturers
> jump on this method of making a universal chip.

It really depends on the voltage divider effect of the transmission line, so
halfway is halfway whether it is 5 or 3 v driver.  But for a a short lightly
loaded PCI bus it may look like incident wave switching anyway,  though the PCI
spec. bases the timing on relflected wave switching however to allow time for
everything to work.

>
>
> William Benner


begin:          vcard
fn:             Bob Mathews
n:              Mathews;Bob
org:            PCDVD
adr;dom:        LSI LOGIC;;1551 McCarthy Blvd.;Milpital;CA;95035;
email;internet: bobm@lsil.com
title:          Application Engineer
tel;work:       408-433-4562
tel;fax:        408-954-4451
tel;home:       pager 800-759-8888 pin 9285254
x-mozilla-cpt:  ;0
x-mozilla-html: TRUE
version:        2.1
end:            vcard