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Re: Bus Clock Speed
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Bus Clock Speed
- From: Ivor Bowden <ivor@peritek.com>
- Date: Wed, 09 Sep 1998 17:25:13 -0700
- Cc: redsp@usa.net
- Resent-Date: Thu, 10 Sep 1998 13:00:22 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"TQ_u81.0.md1.Lnnzr"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
30nS (2.1 Specification: Table 4-5: Tcyc = 30 nS min), so 33 1/3 MHz max
At 03:03 PM 9/9/98 -0400, you wrote:
>Can anyone tell me if the 33 MHz PCI Bus speed is intended to be exactly
>33.0 MHz (33.3333 ns) or if it is actually 33.3333 MHz (30 ns)? I know the
>spec allows for slower operation, but what is the upper limit? I need to
>pick an oscillator for my test circuits.
>
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>Rick Collins
>
>
>reDSP - A Signal Processing Solutions Company
>
>redsp@usa.net
>
>reDSP
>4 King Ave
>Frederick, MD 21701-3110
>301-682-7772 Voice
>301-682-7666 FAX
>
>
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>