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Re: Bus Clock Speed
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Bus Clock Speed
- From: "John R Pierce" <pierce@hogranch.com>
- Date: Thu, 10 Sep 1998 07:40:04 -0700
- Delivered-To: pcisig@teleport.com
- Resent-Date: Fri, 11 Sep 1998 01:30:18 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"eIXF7.0.LQ3.2H-zr"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
>Can anyone tell me if the 33 MHz PCI Bus speed is intended to be exactly
>33.0 MHz (33.3333 ns) or if it is actually 33.3333 MHz (30 ns)? I know the
>spec allows for slower operation, but what is the upper limit? I need to
>pick an oscillator for my test circuits.
I've always run on the assumption that its 33.3333 MHz, so that CPU clock
speeds like 200MHz aren't actually 198 MHz