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Re: Bus Clock Speed
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Bus Clock Speed
- From: Steven Larky <larky@anchorchips.com>
- Date: Thu, 10 Sep 1998 10:35:52 -0700 (PDT)
- Cc: pci-sig@znyx.com
- Delivered-To: pcisig@teleport.com
- In-Reply-To: <199809091904.PAA11930@loas.clark.net> from "Richard Collins - reDSP" at Sep 9, 98 03:03:49 pm
- Resent-Date: Fri, 11 Sep 1998 05:38:28 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"EsCjk2.0.oA5.Zt0-r"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
> Can anyone tell me if the 33 MHz PCI Bus speed is intended to be exactly
> 33.0 MHz (33.3333 ns) or if it is actually 33.3333 MHz (30 ns)? I know the
> spec allows for slower operation, but what is the upper limit? I need to
> pick an oscillator for my test circuits.
>
>
30 ns is the minimum CLK cycle Time. 33.3333 MHz.
See Table 4-5 on page 133 in the PCI 2.1 Specification.
--
Steven
--------------------------------------------------------------
| Steven Larky |
| IC Design Manager Anchor Chips Incorporated |
| Phone: 619-613-7906 12396 World Trade Dr., Ste 212 |
| Fax: 619-676-3911 San Diego, CA 92128-3788 |
| larky@anchorchips.com www.anchorchips.com |
| Winner - Best of Comdex Spring '98 - New Technology |
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