[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: pci extensions (was: *New* PCI bus standard?)
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: pci extensions (was: *New* PCI bus standard?)
- From: "John R Pierce" <pierce@hogranch.com>
- Date: Sat, 12 Sep 1998 09:44:51 -0700
- Delivered-To: pcisig@teleport.com
- Resent-Date: Sun, 13 Sep 1998 04:38:30 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"F88JO1.0.V35.vHg-r"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
>> 1. How feasible is 133MHz bus clocking/signalling
>> really with the current art of silicon? Could
>> you really pump it through a connector or would
>> this be an on-board-only technology?
>
>AGP-1X runs at 66MHz.
>
>AGP-2X is here now, and moves bits twice as fast, effectively 133MHz
>(although the fastest clock/strobe is still 66MHz, but uses both edges).
>All AGP platforms must support this speed.
>
>AGP-4X is in the released spec. Effectively 267M/s data transfer rates,
>using 133MHz strobes. The silicon is different; Vdd is only 1.5V.
>
>All three speeds support connectors.
but they only support ONE connector, its not a bus, its a point to point
connection. I suspect any faster PCI bus technology that supports a backplane
is going to require a seperate port for each slot.