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Questions about PCI-X FAQ
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Questions about PCI-X FAQ
- From: "Eric Rehm" <eric@equator.com>
- Date: Fri, 2 Oct 1998 09:04:11 -0700
- Delivered-To: pcisig@teleport.com
- Importance: Normal
- Resent-Date: Sat, 3 Oct 1998 03:13:02 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"s0W6Y2.0.103.bbF5s"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
In the PCI SIG PCI-X faq (http:/www.pcisig.com/pci_x-faq.doc),
the protocol details
say:
1) Register to register
bus design
2) Transaction byte count
- relaxed ordering rules
3) Split transactions and
non-coherent transactions enabled.
Could someone who define
these a little more clearly, especially
1)?
Is this a move to something more like
ISO/IEC 13213 and IEEE 1394?
/eric