[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
PCI signal integrity problem on passive PCI backplanes
- To: Mailing List Recipients <firstname.lastname@example.org>
- Subject: PCI signal integrity problem on passive PCI backplanes
- From: "Lange, Michael" <email@example.com>
- Date: Wed, 14 Oct 1998 11:16:18 +0200
- Delivered-To: firstname.lastname@example.org
- Resent-Date: Wed, 14 Oct 1998 20:32:59 -0700
- Resent-From: email@example.com
- Resent-Message-ID: <"83AsA1.0.yE3.mk69s"@electra.znyx.com>
- Resent-Sender: firstname.lastname@example.org
first I would like to thank you for all the Email replies I got from
concerning the AMCC DMA bug. The information I got helped us a lot.
I have another question (or issue) concerning the signal integrity
of PCI signals on passive PCI backplanes (and sometimes also on other
We have the following HW scenario here :
- Passive PCI backplane with DEC PCI2PCI bridge chips on it (21152)
and up to 14 PCI slots (made in Taiwan) distributed on 4 PCI bus
of 4 slots each running at 33 MHz (32 bit only)
- slot CPU board (DSM or Motorola for example)
- Windows NT 4.0, service pack 3
- 9-10 PCI add-in cards (DVS cards and non-DVS cards) distributed on
several PCI bus segments
On this system we recognized some stability problems :
Sometimes the CPU hangs, sometimes there are data transfer errors when
between several boards over the PCI bus segments.
These errors are not systematic (for example deadlocks when transferring
data over several PCI bus
segments) but it seems to be a problem of signal integrity, because :
- The error is slot dependent (on some slots the errors occurred and on
some slots not)
- We measured some PCI signals with a HP digital sampling oscilloscope
(500 MHz bandwidth)
and got the following result for the FRAME signal for a single cycle
- In the low phase (should be 1 clock cycle long) there
is a 1 V spike
located dangerously near to the Low-to-High transition
of the PCI clock.
- When the FRAME signal reaches the High level (should
be 3.3 V) there is a lot
of overshoot and ringing (signal goes up to 6 V and
down again to 2 V)
- When we add a capacitor (90 pF) to the FRAME signal on the motherboard
on the PCI segment
it seems to work stable.
- The reason for the bad PCI signals seems to be the layout of the
All PCI signals of the bus segments are driven by the DEC bridge and
routed in parallel over
a distance of (say) 30 cm. The ringing on the signals (which causes
the errors) seems to
be generated due to 2 effects :
- reflections : "reflective wave" protocol seems not to work in
- crosstalk : especially during target reads (switching off
the 32 bit addresses by the initiator)
- Did anybody made the same experience as we did ?
- Does anybody know if there are other companies which produce passive
PCI backplanes ?
We tested another PCI platform made by DEC (seems to work much better
but has a lot of ISA slots
which are not useful for our appplications)
We know that there is a US company named TRENTON which also produces
these backplanes but
do not know how to order them here in Europe.
- The 1 V spike measured on FRAME can also be measured on other PC
platforms (HX,FX for example).
On these platforms all boards (DVS boards and non-DVS boards) seem to
work, but nevertheless :
The +1V spike is located dangerously near to the positive slope of the
PCI clock. You only have
to add additional 50 mV noise and/or jitter on the PCI clock (see
INTEL : spread spectrum clocking)
then you (perhaps) will get problems with your add-in cards.
Does anybody have any comments on this ?
Thanks for your help,
/Michael Lange, Hardware engineer, DVS, Hannover, Germany