RE: PMC BUSMODE#1

[Brooks Lame <Brooks_Lame@mcg.mot.com>]

Per IEEE P1386 Draft 2.0 (is this the latest?), section 6.4.3 Host
Module Logic, the minimum time period between setting BUSMODE[4:2]# and
reading BUSMODE1# is 10 busclock cycles.  It doesn't say so, but it
seems reasonable that this should be done while bus RESET is asserted by
the host.  However, the way it is written, the CMC module's logic
regarding this should be assynchronous.  The CMC module is responsible
for decoding BUSMODE[4:2]# and disconnecting if it does not support the
selected protocol.  So, a PMC module could just decode these and assert
on-card RESET (and deassert BUSMODE1#) if the host protocol is not PCI,
since typical PCI logic tristates when in reset (at least, that's how my
design worked).
--
Brooks Lame'
Design Engineer,  Motorola Monterey Design Center
brooks_lame@mcg.mot.com,  blame@prolog.com
Standard Disclaimer: Editorial viewpoints are not necessarily those of
my employer.

> -----Original Message-----
> From: Tai Phan [mailto:phan@Iphase.COM]
> Sent: Sunday, 11 October, 1998 20:16
> To: Mailing List Recipients
> Cc: phan@rodan.Iphase.COM
> Subject: PMC BUSMODE#1
> 
> 
> Hi,
> 
> I am looking for the timing information of BUSMODE# signals on PMC.
> 
> If these signals are used in the same manner as the PRESENT# 
> pins on PCI, 
> what is the relationship of them to the reset and clock? I intend to
> use the BUSMODE1# to disable the clock to the slot, but if I have to
> wait for the hardware of the PMC to respond, it is too late.
> 
> Any information would be apreciated.
> 
> Regards,
> ----------------------
> Tai Phan                        Interphase Corporation
> phan@iphase.com                 13800 Senlac, Dallas, TX 75234  
> 
>