AW: PCI signal integrity

["Lange, Michael" <lange@dvs.de>]

> -----Ursprüngliche Nachricht-----
> Von:	April, Steven [SMTP:sapril@netcoresys.com]
> Gesendet am:	Thursday, October 15, 1998 2:16 PM
> An:	'lange@dvs.de'
> Betreff:	PCI signal integrity
> 
> Michael,
> 
> We have developed a passive PCI midplane and have experienced
> slot-dependent stability problems however, we did not attribute this
> to
> poor signal quality.  From your description I would be surprised if
> your
> problem is caused by poor signal quality even though you have seen
> cross-talk and ringing on your frame signal.  The reason why I say
> this
> is because you have found that a cap on the frame signal appears to
> fix
> the problem. This tells me that you may have a clock skew problem. If
> your PCI clock trace delay is slightly more than the frame trace delay
> then frame will transition from a low to high before the clock sees it
> at the target.  This is the exact problem I had with some slots.  You
> need to measure the clock-to-clock skew from-to all your devices.  You
> should be running delay-matched single clocks to each device (via
> fanout
> buffer).  If not, it may be hard to fix because you no longer have
> control over clock stubs unless you run rework wire. 
> 
> On my designs I always recover the clock at the plug-in board
> (embedded
> design) with a PLL.  My problem was fixed by adjusting the clock skew
> at
> the PLL until it matched the frame signal's setup and hold at the
> target
> device.   Keep in mind I am oversimplifying this problem because PCI
> cards can also act as masters on the bus thereby presenting a similar
> clock skew problem in the other direction.
> 
	[lange]  I forgot to mention :
	 
	We also use a PLL as clock buffer on one of our boards. But you
must be very
	careful with this, because on LX/BX platforms INTEL introduced a
new technique
	called "spread spectrum clocking". They introduced a Jitter (30
kHz modulation)
	on all clocks to reduce the EMI (electromagnetic interference).
If you have
	a PLL on your board the PLL must "follow" the phase of the PCI
clock. This is a little
	bit complicated to guarantee in practice.

	Do you have any experience with this ? (run your board on LX/BX
platforms).

	PS : you can simply measure the PCI clock jitter with a digital
oscilloscope
	        and enabling a delay of (say) 10 us and look at the
Low-to-High transitions.
	        They will distributed very much in time

	/Michael

> Good luck
> 
> Steven April
> Principal HW Engineer
> NetCore Systems, inc.
> www.netcoresys.com <http://www.netcoresys.com>