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Re: AW: PCI signal integrity
- To: Mailing List Recipients <firstname.lastname@example.org>
- Subject: Re: AW: PCI signal integrity
- From: Ivor Bowden <email@example.com>
- Date: Fri, 16 Oct 1998 13:11:07 -0700
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- Resent-Date: Sat, 17 Oct 1998 07:50:04 -0700
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At 02:34 PM 10/15/98 +0200, you wrote:
>> On my designs I always recover the clock at the plug-in board
>> (embedded design) with a PLL.
>> Steven April
>> Principal HW Engineer
>> NetCore Systems, inc.
>> www.netcoresys.com <http://www.netcoresys.com>
If this was not an embedded design then would not this be non-PCI 2.1
compliant because of requirement 18.104.22.168 note 1): "...must work with any
clock frequency between nominal DC and 33 MHz...the clock frequency may be
changed at any time during operation of the system...the clock may be
stopped in a low state..." ?
No PLL can do that...
i.e. any non-embedded plug in (33MHz) board using a PLL for clock
regeneration is not PCI 2.1 compliant.