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PCI Card Clock Trace Length
- To: Mailing List Recipients <email@example.com>
- Subject: PCI Card Clock Trace Length
- From: Frank Walker <firstname.lastname@example.org>
- Date: Sat, 17 Oct 1998 05:56:42 -0700
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- Resent-Date: Sun, 18 Oct 1998 00:16:54 -0700
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I would greatly appreciate help in the area of the PCI CLK trace layout
shape. To wit:
The 2.1 spec calls for a 2.5" +/- 0.1" trace from connector pad to a
single load. Since the address, data and control lines are constrained
to 1.5" or less, using a standard 21152 bridge chip (or others,
probably) the approximate 1" difference must be made up through the use
of a serpentine (or other) clock trace shape.
Is this the intention of the spec? How are people implementing this?
What is spec-writer's rational for this, given that the extra trace
length will introduce a minimal delay of signal (approx 150ps, min case)
and will result in a longer settling time and greater node capacitance
from the motherboard point-of-view?
Thanks in advance,