Re: PCI Card Clock Trace Length

[Richard Walter <rwalter@corp.auspex.com>]

> 
> I would greatly appreciate help in the area of the PCI CLK trace layout
> shape.  To wit:
> 
> The 2.1 spec calls for a 2.5" +/- 0.1" trace from connector pad to a
> single load.  Since the address, data and control lines are constrained
> to 1.5" or less, using a standard 21152 bridge chip (or others,
> probably) the approximate 1" difference must be made up through the use
> of a serpentine (or other) clock trace shape.
> 
> Is this the intention of the spec?

Yes.

> How are people implementing this? 

By running a squiggly trace from the pad of the chip to the gold finger
that totals 2.5" +/- 0.1"

> What is spec-writer's rational for this, given that the extra trace
> length will introduce a minimal delay of signal (approx 150ps, min case)
> and will result in a longer settling time and greater node capacitance
> from the motherboard point-of-view?

For any synchronous bus, clock skew is a major issue.  You need to make
sure that eveyone on the bus samples & drives at the same time.  For PCI,
the skew requirement is < 2ns when measured at the devices.

The simplest and easiest way to control clock skew is to make all of the
traces from the clock driver to the loads exactly the same length.  However,
a typical motherboard contains some PCI devices soldered on the motherboard
as well as slots for plug-in cards.  So, when routing the clock lines, the
motherboard designer needs to know how much trace length exists on the cards,
so that she can take that into account.  ie: If all the clock lengths from
the driver to the slots is 6.5", then the clock lengths to the soldered
components must be 6.5" + x, where x is the length of the clock trace on
the boards.  The PCI spec explicitly makes x = 2.5".

If the spec did not specify the length x, then different boards would have
different lengths and skew would be greater.  For example, the slowest
allowable propogation deley for signals is 200 ps/in.  Therefore, if you
routed your card's clock trace with only 1.5" instead of 2.5", you could be
adding 200 ps of skew to the clock, and this is 10% of the skew budget.

Note that the clock restriction is +/- 0.1".  This means that making the
clock longer or shorter is bad.  Signal traces, on the other hand are
limited to < 1.5", but there is no minimum.  This is because the clock lines
are point-to-point, while the signal lines are bussed.  This means that every
card on the PCI bus adds a stub to a signal line.  It is pretty much
universally true that stubs are bad for signal quality.  You get
reflections and things.  It is also pretty much universally true that
shorter stubs are better than longer ones (if you've got a discontinuity,
it's better to know about it sooner).  Therefore, bussed signals should be
kept as short as possible, and by making the 1.5" limit a part of the spec,
the PCI writers are providing a known worst-case situation for motherboard
people to use during simulation.

> 
> Thanks in advance,
> 
> Frank Walker
> 

-Richard Walter
rwalter@corp.auspex.com
Note: I speak for myself, not for Auspex.