Re: PCI Card Clock Trace Length

[Ivor Bowden <ivor@peritek.com>]

Yes, this is the intention of the spec, usually the longer length of the
clock trace is implemented through serpentine, or other, pattern. I do not
know the exact rational for this requirement, but you must do it to be
compliant.

At 05:56 AM 10/17/98 -0700, you wrote:
>I would greatly appreciate help in the area of the PCI CLK trace layout
>shape.  To wit:
>
>The 2.1 spec calls for a 2.5" +/- 0.1" trace from connector pad to a
>single load.  Since the address, data and control lines are constrained
>to 1.5" or less, using a standard 21152 bridge chip (or others,
>probably) the approximate 1" difference must be made up through the use
>of a serpentine (or other) clock trace shape.
>
>Is this the intention of the spec?  How are people implementing this? 
>What is spec-writer's rational for this, given that the extra trace
>length will introduce a minimal delay of signal (approx 150ps, min case)
>and will result in a longer settling time and greater node capacitance
>from the motherboard point-of-view?
>
>Thanks in advance,
>
>Frank Walker
>
>
>
-Ivor

Ivor Bowden
Peritek Corp
5550 Redwood Road
Oakland, CA 94619 USA
phone: (510) 531-6500
FAX: (510) 530-8563
email: ivor@peritek.com