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status register bit 15 "detected parity error" for SERR?




PCI spec experts,

In config space, status register [15] states:
    "This bit must be set by the device whenever it detects a parity
     error, even if parity error handling is disabled (as controlled by
     bit 6 in the Command register)."

It is not obvoius if the setting of this bit only occurrs on data phases
or also on address phases.  The wording implies that it is for both.
Reading the Mindshare book on page 198 it clearly states that this bit is
only set on data parity errors (but it isn't the authority/spec for the
bus...).

Should address parity set bit 15 of the status register in addition to
data parity?

-- Neal Palmer

The Dini Group
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