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about rst# signal
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: about rst# signal
- From: sun zhi-gang <zgsun@nudt.edu.cn>
- Date: Tue, 10 Nov 1998 21:38:36 +0800
- Delivered-To: pcisig@teleport.com
- Reply-To: zgsun@nudt.edu.cn
- Resent-Date: Wed, 11 Nov 1998 00:12:53 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"iGuj31.0.C02.D94Is"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
Hello ,
PCI spec. 2.1 says that ' To prevent AD, C/BE# and PAR signals from
floating during reset, the central resource MAY drive these lines logic
loe level'
My question is :
if AD,C/BE# and PAR signals are not drived (let these signals float)
during reset, what will happen? Does it work?
--
*************
Sun Zhi-gang
Section 612, Dept. of Computer Science,
National Univercity of Defence Technology ,
Changsha, Hunan Province, 410073, P.R. China,
Tel: (86-731)4506612(O)
Fax: (86-731)4556650(O)
Email: zgsun@nudt.edu.cn
*************