Re: querries on PCI

["John R Pierce" <pierce@hogranch.com>]

>Answers are welcome for the following querries on PCI and general.
>Here they go.


I'll answer what I can...

>1. We are designing a PCI add on board and is being targetted
>for 25MHz (33MHz was not achievable due to some reasons), 32 bit.
>The user manual for the PC says by changing Dip switch settings,
>25MHz can be set. If I do so, can I get the PCI clock 25MHz practically?
>We are using the Acer make model 920 V55LA.


To run the PCI bus at 25MHz, your processor clock will need to be 50MHz.  The
only pentium shipped with a 50MHz busclock was the 75MHz (of course, you could
run any pentium at this degraded speed, for instance, a 200MHz normally runs
at 66MHz*3 but instead could be run at 50MHz*3 == 150MHz).  I don't know if
Pentium-II systems can be setup this way, they generally run at 66MHz to
100MHz bus clocks (when at 100MHz, the PCI clock runs at CPU clock/3, I don't
think the 440BX chipset has a CPU/4 option).

>2. What is meant by burst mode in PCI? How many data phases it does
>contain? and
>max?


Any number up to rather large.

>3. How to deny the power to the unused CLBs in an FPGA of Xilinx?


no idea.