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RE: Trace length for Interrupt lines
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: RE: Trace length for Interrupt lines
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- Date: Mon, 16 Nov 1998 07:24:12 -0500
- Delivered-To: pcisig@teleport.com
- Resent-Date: Mon, 16 Nov 1998 17:34:50 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"oE8_d.0.np1.Tb1Ks"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
>> I am looking for the rule that governs the trace length for the
>> PCI interrupt signals. Page 154 Section 4.4.3.1 excludes them from
>> the 1.5" rule. Is there a max length for these signal?
>>
>> If my PCI master is behind a PCI bridge, do I need to put a buffer in
>> the interrupt line just to keep the trace from my buffer to
>> the connector
>> short?
> This was/is one of my concerns too. Unfortunately, the PCI Spec
>doesn't say anything other than that PCI interrupts are shareable.
The PCI Spec does say a bit more than that. PCI Interrupt signals are
asynchronous and level sensitive. They are not constrained by timing
like the rest of the PCI bus. Wire delays or gate delays are
unimportant when the signals are asynchronous.