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RE: RE: Trace length for Interrupt lines
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: RE: RE: Trace length for Interrupt lines
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Date: Mon, 16 Nov 1998 20:47:23 -0800
- Delivered-To: pcisig@teleport.com
- Resent-Date: Tue, 17 Nov 1998 14:56:41 -0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"T9J701.0.065.C_FKs"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
> >> I am looking for the rule that governs the trace length for the
> >> PCI interrupt signals. Page 154 Section 4.4.3.1 excludes them from
> >> the 1.5" rule. Is there a max length for these signal?
> >>
> >> If my PCI master is behind a PCI bridge, do I need to put
> a buffer in
> >> the interrupt line just to keep the trace from my buffer to
> >> the connector
> >> short?
>
> > This was/is one of my concerns too. Unfortunately, the PCI Spec
> >doesn't say anything other than that PCI interrupts are shareable.
>
> The PCI Spec does say a bit more than that. PCI Interrupt signals are
> asynchronous and level sensitive. They are not constrained by timing
> like the rest of the PCI bus. Wire delays or gate delays are
> unimportant when the signals are asynchronous.
Sorry, forgot the "duh" stuff. I thought the statement about no max
skew requirement was close enough. Anyway, delays (w/in reason) are
unimportant, but noise may not be.
-- Brooks