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PII NT <-> AMCC S5933 Problem
- To: Mailing List Recipients <email@example.com>
- Subject: PII NT <-> AMCC S5933 Problem
- From: Tobias Stumber <Tobias.Stumber@Fr.Bosch.DE>
- Date: Tue, 17 Nov 1998 12:46:18 +0100
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- Organization: Robert Bosch GmbH
- Reply-To: tobias.stumber@Fr.Bosch.DE
- Resent-Date: Tue, 17 Nov 1998 22:17:11 -0800
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Hi pci experts !
We have developed a PCI plug in card which is something like a frame
grabber and wrote a DOS and NT4 driver for it. With the DOS driver we
didn't have a problem at all. Under NT we found a strange behaviour
when running our application on P2 platforms.
As most of you propably remember there has been a question about
AMCC5933 bus mastering problems when the (BX/LX-)PCI chipsets initiate
special cycles on the pci bus. This was approximately one month ago.
(I attached this mail here just to have the things comlete.)
We now have the same problem with bus master writes from the AMCC to
host memory. Under older Platforms or when running the application
under DOS everything runs errorfree for weeks. But on P2 platforms
running the application under NT4 the AMCC passes a wrong address when
a special cycle (-> master abort) occurred, which asserted the IDSEL
line of the AMCC5933. This line is tied together with one AD[31:11]
line on the motherboard (hostbridge ?).
(Known S5933 error, although AMCC has no 'errata sheet' for that.
They call it a 'design note' !!)
We tried some hardware workarounds:
-Tie the AMCC IDSEL pin to GND before any bus mastering transaction
(with a logic gate)
-Decode CB/E signals to pass IDSEL only when a configuration cycle
is proceeding (with a CPLD)
None of them is PCI compliant, i know. But they work.
Now my questions (I'm surely no NT guru, hope there are some):
-Has anyone experiences with some hw workaround like that ?
-What are these special cycles generated for ?
-Is it allowed to block the IDSEL line while a bus mastering transaction
is in progress or may configuration cycles occur any time ?
And when they do, why ?
-Is there any way to tell NT (or the chipset) not to generate special
cycles on these PC platforms. (On older ones they were obviously NOT
needed.) Perhaps the chipset has some configuration registers we could
Any advice is welcome !
Hope to hear from you soon !
Tobias Stumber Robert Bosch GmbH phone +49-5121-49-2103
FV/SLH-Stumber Postfach 77 77 77 fax +49-5121-49-3910
D-31132 Hildesheim mailto:email@example.com