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Re: PCI Addressing Conventions
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- Subject: Re: PCI Addressing Conventions
- From: 061198 <email@example.com>
- Date: Thu, 19 Nov 1998 16:36:11 -0800
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- Resent-Date: Fri, 20 Nov 1998 10:44:45 -0800
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I may be stating the obvious here: 32-bit PCI has a 32-bit address space.
Your processor must be prepared to address any target, including the host
processor memory *anywhere* in the 32-bit address space.
For example, Compaq/Digital Alpha workstation/server products
use a core logic chipset that has scatter-gather functions (much like
the AGP GART.) Unlike x86, where (usually) host memory
is direct-mapped to PCI (i.e., PCI bus address 0 - 2GB is direct-mapped to
Alpha physical memory address 0-2 GB), on these Alpha platforms,
host memory is accessed via one or more NT-managed translation
windows. In other words, it's quite legal that mapping of xxx MB of
host Alpha memory ranges from physical address 0-2 GB starts at
an arbitrary PCI bus addresses between .5-2.5 GB, i.e., a runtime-dependent
starting address that has a non-zero offset from the the Alpha physical
How will you (i.e. the i960) know? At least on NT, you'll know because
the device driver must map these pages via IoMapTransfer, which
returns a "logical bus address" that represent's the NT HAL's
mapping (via the above-mentioned translation windows) of host memory
to a PCI bus address (said "logical bus address").
There is absolutely no reason that such behaviour is limited to Compaq
Alpha platforms. (Witness the decision by Compaq to use the same
core logic for Alpha and K-6 processors.)
So, the computer world is *not* limited to the x86 direct-mapped model.
Equator Technologies Inc.
Steve Stolper wrote:
> I am new to working with PCI and have a question concerning existing
> adressing conventions (if any).
> We have a board which resides in the PCI back-plane of a personal
> computer. The board contains a microprocessor (i960) which has two
> modes of addressing memory across the PCI bus.
> The first is a "direct addressing" method which asserts the same
> address on the PCI bus that was issued on the local bus. The second is
> an "addressing window" method which uses a register to translate the
> address before placing it on the PCI bus.
> We are currently employing the direct addressing method to access
> memory on the PC host across the PCI bus. We have not experienced any
> problems but wonder if we have just been lucky. The direct addressing
> method only allows access to PCI addresses in a 2 gigabyte window. The
> PC has always placed its memory within this window on the PCI bus.
> Is it a convention that a PCI bus master (the PC) places its own memory
> into the lower 2 gigabytes or have we simply been lucky?
> We had assumed that the (i960) direct addressing mode would allow us to
> be consistent with the PCI bus standard. Is this a faulty assumption on
> our part?
> Do we have to utilize the "addressing window" approach to be consistent
> with the PCI bus standard?
> Thank you very much for your assistance.
> - Steve