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Re: Sharing PCI configuration memory



>Q1) If a device is at the same time, Master and Slave PCI, is it required to
>have a double configuration memory area i.e. one for the Slave part and
>one for the Master one ?

Master and slave are operation types, not devices.  All masters have to accept
slave operations to, thats how you program them, set them up.  A master is
simply a device that issues its own read/write commands to other PCI devices
(or the host memory) in addition to acception read/write cycles.

>Q3) Suppose that I have a PCI Master/Slave device, whose PCI configuration
>RAM area, can be configured by an application non-PCI bus, driven by an
>external CPU.
>
>Suppose now that I want at Power On Reset (POR, so it is not an on the fly
PCI
>device characterization) to configure PCI configuration
>RAM area either as Master/Slave or as Slave only.
>
>Is there a way to tell to a PCI Software configuration Driver, insuring
>that a minimum
>set of configuration area location is ready at POR, to retry configuration
>cycles
>until the external CPU complete the initialization of the PCI configuration
>RAM ?

I believe so, you just hold off acknowleging any config cycles until you have
completed internal initialization.  Ideally, this shouldn't take very long, as
it will stall the host processor

>Q4) In case A3 is positive which is this minimum set (registers/bit names
>according to PCI
>2.1) of Configuration Area ?

You would have to set pretty much all the 'static' configuration information
(device class, PCI device ID, any internal bits that enable/disable writing
the aperture size bits in the various base registers.

>Q5) Is there a WEB node where I can find the preliminary/draft version (a
>detailed Document
>rather than the one listed in the PCI SIG WEB page) of what will became PCI
>2.2
>standard i.e. PCI compatible with MicroSoft 99 specs ?

You need to be a full PCI-SIG member to have access to working drafts.

-jrp