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Newbie question about PCI interrupts
- To: Mailing List Recipients <email@example.com>
- Subject: Newbie question about PCI interrupts
- From: "George Pauley" <firstname.lastname@example.org>
- Date: Wed, 6 Jan 1999 16:39:44 -0700
- Delivered-To: pcisig@teleport.COM
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- Resent-Date: Wed, 6 Jan 1999 16:15:20 -0800
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I'm new to PCI, and am sure this is a stupid question, but I can't glean
this information from
the PCI spec or any of my other sources. Thanks in advance for your help.
We are building a custom computer device which will act as a PCI host
controller. (We are
using a PCI bridge chip from V3 as our interface to the PCI bus.) The
system is not x86
based, so my question is PCI specific, not PC/ISA specific. We are using
(if that is pertinent).
The general question is:
How do I process interrupts from the PCI bus? What is the process for
More specifically, here are some of the issues which are confusing me...
INTA thru INTD are ORed by the bridge chip and will signal a single
interrupt on the CPU.
Presumably my ISR will have query each PCI device on the bus to determine
caused the interrupt. Since this information is (typically) located in the
portions of the configuration ROM, the ISR will have use each device's
driver to determine
this information. Furthermore, each device driver will be required to
cause the device to
relinquish its INTx line.
Since the INTx lines are level triggered, if I get two interrupts
simultaneously, and clear
one interrupt, presumably the second device will still be holding the INTx
line low. How
does the bridge chip know that this is a 2nd interrupt?
Now we might say that my ISR should query each device to see if it has an
interrupt. But querying is not a discrete instruction. I could query a
while I'm querying the next device, I could get an interrupt on the 1st
do I handle these situations.
Finally, what is the Interrupt Acknowledge cycle all about? Is this what
bus to allow future interrupts? The cycle returns a vector, which appears
to be the
Interrupt Line value determine during configuration. Since the cycle is a
with no address, which card responds with a vector? The spec says the
cycle is implicitly addressed to the interrupt controller. Well how does
controller know what vector to return?
It should be obvious by now, that what I really need is someone to go
interrupt cycle step by step for me. If you can recommend a good book, or
which can give me this information that would be great too.
I appreciate the help. I'm a bit disappointed in the spec which goes
through read and
write cycles in great detail, but forgets to discuss this issue. Guess I'm
supposed to use PCI in a x86 PC system which already has all this stuff
the hardware! <grin>