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RE: Reading Base Address Registers
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: RE: Reading Base Address Registers
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Date: Fri, 8 Jan 1999 20:41:38 -0800
- Cc: "'PCISIGList'" <pci-sig@znyx.com>
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- Resent-Date: Fri, 8 Jan 1999 21:06:35 -0800
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Uh, how about zeros? See implementation note in section 3.2.2.
-- Brooks :\
> -----Original Message-----
> From: Scott C. Karlin [mailto:scott@CS.Princeton.EDU]
> Sent: Friday, 08 January, 1999 14:57
> To: Mailing List Recipients
> Subject: Reading Base Address Registers
>
>
> This question deals with section 6.2.5.1 of Rev 2.1 of the PCI Spec.
>
> According to the spec, "a type 00h predefined header has six DWORD
> locations allocated for Base Address registers starting at offset
> 10h in the Configuration Space."
>
> It seems clear how to read each base address register and determine
> whether it is for memory or for I/O.
>
> How does one determine if a location represents a valid base address?
> That is, if a particular device only needs one of the six base
> address registers, what must be put in the remaining five locations
> to indicate that there are no more needed base address registers?
>
> Thanks,
> Scott
>
> --------------------------------------------------------------
> ------------
> Scott C. Karlin Princeton University
> Graduate Student Department of
> Computer Science
> Voice: (609) 258-5386 35 Olden Street
> Email: scott@cs.princeton.edu Princeton, NJ 08544-2087
> WWW: http://www.cs.princeton.edu/~scott
> --------------------------------------------------------------
> ------------
>