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Re: multi function answers



Phillip:

I aprreciate your prompt help, many thanks. I still have some confusions,
hope you can help me clear them.

>  > In the description of configuartion space (PCI 2.1) it is mentioned
that a
>  > device may have multiple functions and each of the functions will need
to
>  > implement its own configuration space, and also there is a bit (bit 7
in
>  > header type) in the configuration space that should be turned on when
its a
>  > multifunction device.
>  >
>  > But i guessed i have missed where it specifies how the confugaration
spaces
>  > are laid out in a multifunction device, can anyone shed some light on
this?
>
>The same way as a non multi-function device. I.e., think of the
>"address so to speak" of ANY PCI device to be bus number,
>device number, function number. Thus, a singlem function device
>only has, but always has, function 0.
>

This is the logical view of the functions, as the function hierarchy is
presented to the system. I was trying to get a better idea how the
configuartion space for each function is mapped within a device's
configuration space, sort of like a crude memory map would help clear my
undersatnding. As per the document it seems like we need a 256 byte header
for each function. For a single function device, the map is apearent-

config
address         desctiption
======         =========
0: function0_header
256: function0_trailer

What is the map for a multifunction device? How does one tell the address of
configuration registers of the next function in the device config space, how
does one tell how many function are present in the device configuaration
space?

>  > Also how does the bios find out how many functions the device supports
in
>  > case its multifinction device and what are the class codes for each of
the
>  > functions (which may be a redundent question as above)?
>
>The best pragmatic way to to see if the bendor and device ids are valid.
>Then, if it uses the BARs, if BAR 0 can be sized.


My understanding is BARs are used for multiple memory windows for the same
function. Is this interpratation wrong? Can you please elaborate more on
this? how does BAR sizing tell bios how many functions are present on the
device?

Best regards,
Khan Kibria
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