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RE: PCI Compliance of PLX's PCI 9054 I/O buffers
- To: Mailing List Recipients <email@example.com>
- Subject: RE: PCI Compliance of PLX's PCI 9054 I/O buffers
- From: Douglas Gilligan <firstname.lastname@example.org>
- Date: Wed, 14 Apr 1999 12:29:35 -0700
- Delivered-To: pcisig@teleport.COM
- In-Reply-To: <00008DDF16DFD211ACB400A0C9CA419E0AF0A6@SVSR-NT01>
- Resent-Date: Wed, 14 Apr 1999 13:03:19 -0700
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- Resent-Message-ID: <"SyI4G1.0.fW3.xoE5t"@electra.znyx.com>
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I noticed that 4.2.1 is referring to the 5V signaling environment,
whereas 4.2.2 covers the 3.3V signaling environment.
I see no conflict. In the 5V signaling environment "The upper clamp
is optional," whereas in the 3.3V signaling environment "Inputs are
required to be clamped to BOTH ground and Vcc (3.3V) rails.".
This clearly implies that for either a 3.3V or Universal signaling
environment, clamping to the Vi/o allows the board to remain in spec.
By not clamping to a power rail, PLX is failing the spec even though
they may still be functional. I note that PLX does not connect to
the Vi/o PCI power pins. As I understand it, this spec issue is why
the Vi/o pins are in the spec and on the connector.
The electrical characteristics of the PCI bus are complex enough that
I for one would be more comfortable with a device that conforms to the
spec than one who treats it as a recommendation.
>Our 5V tolerant 3.3V PCI device (PCI 9054) complies with PCI spec
>in the 3.3V signaling environment in the sense that it meets most
>of the DC and AC electrical specifications in that environment.
>PCI Specification Rev 2.2 did specify High and Low Clamp Current
>limitations (Table 4-4 of section 126.96.36.199) for 3.3V signaling. I
>do not interpret these specifications as hard rule for compliance
>to PCI Specification.
Or that change the design parameters in ways that in a generic
system may have unexpected complications.
>It is also true that a diode clamp to VDD would help reduce high
>signal levels caused by reflection as they travel along traces on
>This type of problems, however, are more readily solved by designing
>trace impedance to match the output impedance of the drivers. 9054
>should handle trace impedance between 40 to 70 ohms without problems.
I understand a company wanting to rely on checklists and outside audits,
but these are just aids. Compliance is not a matter of forms, it is a
matter of electrical characteristics. I am not an analog guru, and I
welcome hearing from one as to why and how the spec should be changed.
I have a hunch the reason this has not yet become critical is that
most systems are still 5V signaling environments even when all of
the components on the bus are 3.3V devices. This may well become an
issue with the next generation of parts powered at lower voltages if
they have difficulty retaining 5V signalling environment capability,
forcing the predicted migration to 3.3V signalling environment systems.
At 09:48 AM 4/14/99 -0700, you wrote:
>"The specification cannot be more clear on this point than it is."
>188.8.131.52 page 120 paragraph 2
>"Inputs are required to be clamped to ground"
>184.108.40.206 page 121 bullet 3
>"The upper clamp is optional,"
>Now you may disagree with the spec, but it is clear. But also consider the
>case when a part or card is not installed. In that case, there are no
>clamping diodes at all.
>From: O'Shea, David J [mailto:email@example.com]
>Sent: Tuesday, April 13, 1999 6:01 PM
>To: Mailing List Recipients
>Subject: RE: PCI Compliance of PLX's PCI 9054 I/O buffers
>It struck me from the original poster's comments that
>he and (not PLX) was quite correct about the non-compliance
>of the PLX device despite any marketing-eeze presented below
>about compliance workshops, buffer designs, etc.
>His comments correctly went to the lack of proper clamp
>diodes on the device. These are necessary to protect other
>devices on the bus, and to protect the system power supply.
>They are not necessarily just for the protection of the PLX's
>own I/O driver/buffer cells. The specification cannot be
>more clear on this point than it is.
>I think anyone who has ever designed this stuff knows the
>truth of it, and PLX does itself a huge dis-service by just
>ignoring the issue and "claiming" compliance.
>Go take the dog and pony somewhere were there are not
>engineers in the room. Its very annoying at best.
>> -----Original Message-----
>> From: Bill Brisko [SMTP:firstname.lastname@example.org]
>> Sent: Tuesday, April 13, 1999 2:32 PM
>> To: Mailing List Recipients
>> Subject: PCI Compliance of PLX's PCI 9054 I/O buffers
>> A recent posting to the PCI SIG reflector stated that PLX
>> Technology's PCI 9054 I/O universal 3.3V/5V buffers were
>> not compliant to the PCI 2.2 specification.
>> We want to make it clear that these buffers are compliant
>> to the specification. PLX designed these buffers to be reliable
>> under the worst case voltage transient conditions.
>> The PCI 9054 has passed all tests of the PCI Compliance
>> Workshop. The PCI compliance checklist, which included a section
>> on the I/O buffer design, has been submitted and recently approved
>> by the PCI SIG (special interest group). Thus, the PCI 9054 is
>> PCI 2.2 compliant and will be listed on the PCI Integrators list
>> when it is updated in the near future.
>> If you have any questions on this subject, please feel free to
>> contact our Technical Application Engineering Dept at 408-328-3531
>> Mike Hopwood
>> VP, World Wide Sales