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Cirrus Logic GD5465 Unreliable Operation
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- Subject: Cirrus Logic GD5465 Unreliable Operation
- From: "Dremann, Jeffrey E" <Jeffrey.Dremann@unisys.com>
- Date: Tue, 22 Jun 1999 10:11:51 -0400
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- Resent-Date: Tue, 22 Jun 1999 07:59:31 -0700
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I need assistance/suggestions on how to resolve this. Has anyone had a
similar problem with the Cirrus GD5465 on PCI? We have not had luck with
Cirrus/iSD so far.
1. GENERAL PROBLEM DESCRIPTION
The general problem we are attempting to solve is unstable and unreliable
functionality of a Cirrus Logic GD5465, PCI, 3D graphics accelerator chip.
The failures are in the area of basic ability to communicate with the
controller and establish basic functional operation, including proper
initialization. Internal registers occasionally do not operate, read of the
BIOS ROM is unreliable, and it appears to initialize differently at various
2. GD5465 HARDWARE CONFIGURATION
The GD5465 is configured as follows:
a) It is configured as a PCI device (rather than AGP).
b) BIOS ROM is enabled. A BIOS ROM is connected to the ROM interface.
c) BIOS ROM size = 32K.
d) PCI bus clock speed is 33MHz
e) XTAL freq = 14.318 MHz
f) Video dot clock freq ??? (or just RAMBUS clock) is 257 Mhz. This is
the standard recommended configuration with a value of 12h in the BCLK MULT
g) PCI signaling: 3V.
3. PCI BUS
3.1 PCI BUS DEVICES ATTACHED
The PCI bus on which the GD5465 resides has the following devices attached:
a) DEC21152 PCI-PCI Bridge secondary PCI interface.
b) Intel i960RD Processor primary PCI interface.
c) Adaptec AIC7897 SCSI controller.
3.2 PCI BUS OPERATIONAL INTEGRITY
The PCI bus on which the GD5465 is located is capable of normal operation
between PCI devices other than the GD5465. The I960 processor is able to
perform PCI configuration, internal register tests and a SCSI Control Block
RAM test to the AIC7897 without failure. Therefore, it is believed that the
bus timings, pull-up resistors routing etc are satisfactory on this bus.
The PCI bus signals have also been probed during operation and both signal
quality and timing appeared to have plenty of margin.
4. IMMEDIATE GD5465 TEST FAILURE
We are currently attempting to have the i960RD processor successfully read
the BIOS ROM over PCI with the GD5465 as a target. The BIOS ROM is 32K in
size. We are consistently able to read about 5K bytes of the 32K, and then
gross functional failure occurs. There are two failure modes:
a) The GD5465 does not assert DEVSEL to the READ request. The PCI
cycle is, therefore, not claimed and the I960 master then does a MASTER
ABORT. At times the master attempts to resume the test, but quickly fails
with failure mode b), next.
b) The GD5465 issues TGT RETRY continuously. The test hangs with the
READ transaction never completing, but a continuous stream of the master
issuing the READ and the GD5465 responding with TGT RETRY.
Before either of these failures occurs, it was noted that the GD5465 changed
its DEVSEL timing from MED to FAST. This DEVSEL speed change was also
readable in the _______ status register. It is unknown what causes this
change of timing to occur.