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- To: Mailing List Recipients <email@example.com>
- Subject: Unidentified subject!
- From: "Stephan Rosner" <firstname.lastname@example.org>
- Date: Tue, 27 Jul 1999 04:31:29 +0200
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- Resent-Date: Mon, 26 Jul 1999 20:02:29 -0700
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I ran into the following question, where I did not find an
answer in the documentation. Therefore, I would appreciate
if somebody could help out.
A PCI device supports the power states D0 and D3hot/cold.
If SW requests D2 or D1 discarding that this is disabled
in the configuration space, a "graceful" response is
asked in the spec. To what value have the power state regs
bit[1:0] in PMCSR to be set?
- D3 or D0 since the device does not support D2/D1
- D1/D2 and the device acts as if it would be in D3
- something else
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