66 MHz Timing : Clock to Output Paramter

[Raghunath Tilak <Tilak@ambernetworks.com>]

Hello,
I have 2 questions related to the 66 MHz timing parameters.

*	
I am trying to estimate the clock to out delay for PCI pads.
The test conditions for a 66 MHz PCI say that the load on the pin is 10
pF.
( fig. 7.5 and 7.6 in PCI Specs Rev 2.2 )
At this condition, the maximum Clock to Output (Tval) parameter is 6 ns.

I was wondering whether 10 pF is really the case or in practice the load
is
much more than 10 pF. Our system design engineers say that the load 
could be as high as 30 pF for 3 edvices. ( "Add extra 10 pF if you have
a connector")

This means that if I really want to see whether the pads are in
agreement with
the PCI specs, I need to check them at 10 pF load.
When I use 30 pF load to find out the delay of the pads, it causes the
PCI 
clock to output time constraint violation.

In practive the load on a PCI pin would be higher than 10 pF. So it may
reduce the 
maximum frequency at which the PCI bus can operate.

Is this a known issue or I am missing someything?

*	The temparature at which the paramters reach their maximum
values

	This is not mentioned in the Specs.
	The delay of the pads will increase with the temperature. So the
6 ns
	constraint is really with Highest Temperature allowed for the
commercial parts
	with slow process and low voltage settings.
	Is this interpretation correct?
	

Thanks for your time,
Raghu Tilak