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PAR64
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: PAR64
- From: "Kjell A. Andersen" <kjell@vmetro.no>
- Date: Mon, 09 Aug 1999 13:44:32 +0200
- Delivered-To: pcisig@teleport.COM
- Organization: VMETRO asa
- Resent-Date: Mon, 9 Aug 1999 05:27:20 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"VPVzI2.0.1G4.61iht"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
Hi,
In PCI spec. 2.1 PAR64 was only required to be valid "one clock after
the initial address phase when REQ64# is asserted and the DAC command is
indicated on C/BE[3::0]#. PAR64 is also required to be valid the clock
after the second address phase of a DAC command when REQ64# is
asserted."
In PCI spec. 2.2 "PAR64 must be valid one clock after each address phase
on any transaction in which REQ64# is asserted." I.E. PAR64 must be
valid one clock after each address phase regardless of the DAC command.
Does anyone know the reason for this PAR64 spec. change?
Regards,
Kjell A. Andersen
--
VMETRO asa
Kjell A. Andersen
Brynsveien 5
0667 Oslo, Norway
Tel: +47 22106090
Fax: +47 22106202
email: kjell@vmetro.no
http://www.vmetro.com