PCI buffers and 5 volt tolerance

[tchoug <tchoug@micron.com>]

I've reviewed several ASIC vendors 5 volt tolerant PCI buffers implemented
in a 3.3 volt process. It seems there are several different interpretations
of what a universal PCI buffer is and what "5 volt tolerant" means. I've
also followed several discussions in this group in the past regarding
universal PCI buffers and 5 volt tolerance. But what seemed to be missing
from these discussions are how ASIC vendors are actually implementing these
buffers and do they really meet the spec.

The definition of "5V tolerant" is pretty clear in the PCI specification as
a device which can sustain the 11 volt overshoot. For a 5-volt device the
clamping diode is optional based on the tolerance of the 5 volt process to
the overshoot. In reference to 3.3 volt devices on a 5 volt PCI bus the PCI
spec makes the statement "For devices built in 3 volt technology, the upper
clamp is, in practice, required for device protection." This diode, if
present, is required to be clamped to the 5 Volt supply - not 3.3 volt. 

One implementation I've seen dedicates an internal connection to the I/O
buffer specifically for the clamping rail. These connections are bussed
together for all PCI buffers and connected to device pins which are
externally connected to the appropriate clamping voltage. When operating in
a 5V environment these would connect to 5V for appropriate input clamping.
Likewise when operating in a 3.3V environment these would clamp to 3.3V. The
penalty here is that in order to sink sufficient current (around 100
milliamps instantaneous per PCI pin), there needs to be a large number of
pins dedicated to this clamping rail.

Other implementations I've seen have a control input to the buffer that
selects between 3.3V clamping and no clamping for 5V environments. I
seriously question the ability of these devices to tolerate the specified
11V for 11 nsecs as specified in the PCI spec. Even though I believe this
spec to be highly on the conservative side (i.e. observing this reflection
for 11 nsecs in a real system would be highly unlikely), I have a hard time
believing that 3.3V buffers could tolerate this voltage for any period
without some form of clamping.

Without naming names, what have others observed regarding ASIC vendors
universal buffers and claims of 5 volt tolerance?
Is there a solution that does not require a large number of seperate
clamping rail pins?
Are some ASIC vendors ignoring the 11V for 11 nsec tolerance requirement or
desiging for a more realistic duration?
Are any ASIC vendors clamping to the 3.3 volt rail through a diode stack or
gated device that prevents clamping below 5 volts?

Thanks,
	Todd Houg