PCI Questions

[Raan Kahn <raan@ngcable.com>]

Hi,

Again we have some Question:

1) As a target device on the PCI, we only support 1 word bursts.
How can we inform the master that it is not allowed to access us with
more than 1 word bursts (for read and write)? I know that one way is for
us (as target) to issue a disconnect A or B during the first data phase
or disconnect C in the second data phase. This is not possible for us to
do.
I am wondering if there is another way to inform the master, maybe
through the driver/configuration register.

2) I/O address space.
Our I/O registers are 32 bit registers.
When a master accesses our I/O, are the addresses for the I/O space
long-word aligned like the memory address space (address 0'h0, 0'h4,
0'h8.... ) ?

3) I/O address space.
Are there any I/O addresses reserved or commonly used, that we should
not use in our chip?
Is it O.K to use offset address 0 and offset address 4 (or 0 and 1 -
depending on the answer to question 2)?


Thanks.

Raan.