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Transaction ordering
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Transaction ordering
- From: ervhom@erv.ericsson.se (Magnus Homann)
- Date: Wed, 11 Aug 1999 13:56:34 +0200
- Delivered-To: pcisig@teleport.COM
- Resent-Date: Wed, 11 Aug 1999 05:33:16 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"-k5R31.0.ce.3OMit"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
Hello,
In the PCI 2.1 spec it says that the (host bus?) bridge must flush
all its posted writes in both directions before completing a read
transaction. At least, that's my intrepretation of chapter 3.2.5 (3),
first paragraph.
If I'm right in the above, why is it necessary to flush all posted writes
in *both* directions before completing a read. Can somebody enlighten me?
Yours,
Magnus Homann