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PCI Questions, Yet Again
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: PCI Questions, Yet Again
- From: Raan Kahn <raan@ngcable.com>
- Date: Sun, 15 Aug 1999 18:12:42 +0200
- CC: raan@ngcable.com
- Delivered-To: pcisig@teleport.COM
- Reply-To: raan@ngcable.com
- Resent-Date: Sun, 15 Aug 1999 08:59:44 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-ID: <"8fegv2.0.-h6.icjjt"@electra.znyx.com>
- Resent-Sender: pci-sig-request@znyx.com
Hi,
Again we have some issues we can not figure out:
1) Prefetchable bit in the Memory Base Address configuration register.
What does it mean and how does it influence the target ability to
support (or not support) data burst transactions?
2) Cashable/non-cashable memory: what does it mean regarding the PCI
host and how does it influence the target ability to support (or not
support) data burst transactions?
Thanks...
Raan.