RE: 66 MHz Timing : Clock to Output Paramter

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

Raghu Tilak writes:

>I am trying to estimate the clock to out delay for PCI pads.
>The test conditions for a 66 MHz PCI say that the load on the pin is 10
>pF.
>( fig. 7.5 and 7.6 in PCI Specs Rev 2.2 )

Actually, the bulk of the load is the 25 ohm resistor.  The 10 pF allows you
to have stray capacitance in your test equipment.

>I was wondering whether 10 pF is really the case or in practice the load
>is
>much more than 10 pF. Our system design engineers say that the load 
>could be as high as 30 pF for 3 edvices. ( "Add extra 10 pF if you have
>a connector")

The actual load does indeed exceed 10 pF, if you add it up like a lumped
load.

Two things:

(1)  Forget about lumped loads.  Think transmission lines.  Three devices at
10 pF each, plus X inches of trace at Y pF/inch, does not behave like an
equivalent 30+ pF lumped capacitor.

(2)  Pay close attention to how bus propagation times are specified (section
7.7.5).  The bus (or "wire") delay includes the difference between the test
load (25 ohms & 10 pF) and the actual bus load.  Thus, the difference
between 10 pF and 30+ pF is accounted for in your Tprop ... not in your
Tval.

>*	The temparature at which the paramters reach their maximum
>values
>
>	This is not mentioned in the Specs.
>	The delay of the pads will increase with the temperature. So the
>6 ns
>	constraint is really with Highest Temperature allowed for the
>commercial parts
>	with slow process and low voltage settings.
>	Is this interpretation correct?

I think that is generally the case for most CMOS devices.  However, there
could be exceptions.  The timing specs should be met across the temperature,
process, and supply voltage range.  You figure out how to make your devices
fit within that window.

Regards,
Andy Ingraham