RE: PCI buffers and 5 volt tolerance

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

Todd Houg writes:

>I've reviewed several ASIC vendors 5 volt tolerant PCI buffers implemented
>in a 3.3 volt process. It seems there are several different interpretations
>of what a universal PCI buffer is and what "5 volt tolerant" means. I've
>also followed several discussions in this group in the past regarding
>universal PCI buffers and 5 volt tolerance. But what seemed to be missing
>from these discussions are how ASIC vendors are actually implementing these
>buffers and do they really meet the spec.

That may be because they consider it proprietary.

>Is there a solution that does not require a large number of seperate
>clamping rail pins?

Probably, yes.  Be creative.

>Are some ASIC vendors ignoring the 11V for 11 nsec tolerance requirement or
>desiging for a more realistic duration?

I don't know ... but if there is any kind of clamping in their PCI buffers,
whether via explicit clamp diodes or some other breakdown, the maximum
voltage at the pins will be less than 11V.  Breakdown is good if it doesn't
damage the part.  The buffer just needs to tolerate it without permanent
damage.

>Are any ASIC vendors clamping to the 3.3 volt rail through a diode stack or
>gated device that prevents clamping below 5 volts?

Clamping to the 3.3V rail carries some risk because the current goes the
"wrong way" out the 3.3V supply pins.  The 3.3V regulator design needs to
take that into account.  Taking the clamp current to ground would be more
foolproof for the ASIC user.

Regards,
Andy Ingraham