RE: FPGA's and PCI

["Olsen, Kim" <KOlsen@acdnj.itt.com>]

Jeff,
I don't totally agree with you.  An FPGA solution is simple enough for a
register access system for target reads and almost any type of target write.
Initiator operation become a bit hairy to deal with.  
What I have found is the most difficult implementation for FPGA based PCI
interfaces is a PCI to local bus bridge.  In this case you have many
potential bottlenecks to avoid, especially when the device may be targetted
by several initiators.  The latency from the local bus to the PCI bus may
cause data to be read from the local bus into a PCI interface buffer too
late for the transaction to pass to the PCI system (master abort, initial
latency timeout, etc.).  In this case the data must be held for the next
time that a master reads from the same address.  If another master attempts
to perform an operation you need to handle the transaction in such a way the
you don't discard that data.  This is of course a requirement for reads that
are non-prefetchable, i.e. the reads operation causes some side effect.  If
the reads are always prefetchable then you can discard the data and re-read
it later, assuming you will not get into a situation where the read always
takes too long to be able to present data to the PCI system, in which case
you have a dead lock.  In cases like this then a complete PCI interface
device would be quite useful.

So, as you noted there are a lot of little things to deal with, but if the
backend system is simple enough then the FPGA solution is quite viable.

Kim

-----Original Message-----
From: Neal Palmer [mailto:neal@dinigroup.com]
Sent: Thursday, August 26, 1999 3:00 PM
To: Mailing List Recipients
Cc: Mailing List Recipients
Subject: Re: FPGA's and PCI



Jeff,

   I wouldn't recommend using an FPGA to implement your PCI design, unless
there is some feature that you absolutely require that you can't get in
some other device.  All of the major FPGA vendors have soft-cores that
implement PCI functionality, but you will find that there are lots of
subtle details on PCI that those cores have chosen to ignore, such as the
Xilinx core requires you to remember the last 3 pieces of data that you
have sent to pci in case they didn't ever get there.  Plus we have found
that the price for the FPGA solutions are far more expensive than buying a
stand alone PCI controller and a CPLD for control signals on the PCI
controller.

   I would suggest that you look at a stand alone PCI controller from PLX,
Galilelo, Tundra, AMCC, or V3 (and then ask about specific problems on the
chip you have chosen).  As another though, you might consider either of
the FPGA+ASIC Core chips from QuickLogic or Lucent, because they have done
all of the work of making PCI do the right stuff (just like the stand
alone controller companies above), plus they might allow you to get down
to a single chip solution.

   You also asked about how difficult was it to implement the pci
interface.  PCI is not simple.  You want somebody else who has already
done it a few times to do it for you.  There are so many little details
that you have to worry about that you most likely would still be finding
problems with different PCI systems in a year or two after you have
finished desiging it, if you were to do it yourself.

   If you want more detailed information, then please contact me.

On Thu, 26 Aug 1999, Jeff Leine wrote:

> I am currently working on a preliminary design of a PCI card.  I want to
use an
> FPGA to implement a PCI interface as well as most of the design
functionality.
> I would be interested in hearing from anyone who has used an FPGA as a PCI
> interface.
> 
> How difficult was the implementation of the PCI interface in the FPGA?
> 
>  What kind of issues were there?
> 
> Any other information that might be of interest would also be appreciated.
> 
> Thanks in advance,
> 
> Jeff Leine
> 
> 

-- Neal Palmer

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