Re: What if BASE0 is not implemented?

[Richard Walter <rwalter@corp.auspex.com>]

> 
> Lame Brooks-G14738 wrote:
> > 
> > I was under the impression that BARs should be impemented in consecutive
> > order from 0, but don't recall the reference for that.
> > -- BrooksL
> 

I had the same impression (that BARs needed to be implemented in order), but
I looked in the 2.2 spec quickly this morning and couldn't find it.

However, just so that other people don't think that they're going crazy
either, I did just go back and find these:

PCI 2.1, section 6.2.5.1., page 197, paragraph 4, sentence 2:
"The first Base Address register is always located at offset 10h.  The
second register may be at offset 14h or 18h depending on the size of
the first.  The offsets of subsequent Base Address registers are
determined by the size of previous Base Addresss registers."

and PCI 2.2, section 6.1.5.1., page 204, paragraph 1, sentence 2:
"A device may use any of the locations to implement Base Address
registers.  An implemented 64-bit Base Address register consumes two
consectutive DWORD locations.  Software looking for implemented Base
Address registers must start at offset 10h and continue upwards
through offset 24h."

It would be nice if someone who was involved in this change from 2.1
to 2.2 would explain why things have changed.  It seems to me that
the net result of this change is to possably invalidate alot of
existing 2.1 configuration software for no real gain at all. *sigh*

-Richard