Expansion board decoupling specs

[Craig Rich <craig_rich@sundanceti.com>]

Hello:

	I am currently designing a 64 bit/66MHz PCI expansion board and have a
question regarding the decoupling requirements stated in section 4.4.2.1
of the PCI Spec rev 2.2.

	In section 4.4.2.1, there is a statement regarding decoupling of unused
power pins to ground via 0.01uF per Vcc pin. On our board we are only
using the +5V power pins, and thus have many unused power pins (all 3.3V
and all VI/O pins). Adding the capacitors as apparantly required by the
specification is making trace routing difficult. Is there a better way
to achieve compliance than adding capacitors? For example, could a power
plane (in parallel with a ground plane) achieve the desired per pin
capacitance required by the spec in an area feasible on an expansion
board?

-- 
Craig Rich
Senior Systems Engineer         mailto:craig_rich@sundanceti.com
Sundance Technology Inc.        http://www.sundanceti.com
1485 Saratoga Avenue            tel: 408 873 4117 x107
Suite 200                       fax: 408 996 7064
San Jose, CA, USA  95129