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Why was this changed in 2.2? RE: What if BASE0 is not implemented?
I agree. The only reason I can think of for this change between 2.1 and 2.2
is to allow some devices that were not 2.1 compliant, to be compliant under
2.2. This is _not_ a good reason. If I were writing BIOS or other config
software, the 2.1 requirement is cleaner and allows config algorithms to be
faster since they can stop upon finding an unimplemented BAR. So, the
question remains, why was it changed? And, do all the BIOS writers realize
that it was changed? -- BrooksL
> > > I was under the impression that BARs should be impemented
> in consecutive
> > > order from 0, but don't recall the reference for that.
> > > -- BrooksL
> >
>
> I had the same impression (that BARs needed to be implemented
> in order), but
> I looked in the 2.2 spec quickly this morning and couldn't find it.
>
> However, just so that other people don't think that they're
> going crazy
> either, I did just go back and find these:
>
> PCI 2.1, section 6.2.5.1., page 197, paragraph 4, sentence 2:
> "The first Base Address register is always located at offset 10h. The
> second register may be at offset 14h or 18h depending on the size of
> the first. The offsets of subsequent Base Address registers are
> determined by the size of previous Base Addresss registers."
>
> and PCI 2.2, section 6.1.5.1., page 204, paragraph 1, sentence 2:
> "A device may use any of the locations to implement Base Address
> registers. An implemented 64-bit Base Address register consumes two
> consectutive DWORD locations. Software looking for implemented Base
> Address registers must start at offset 10h and continue upwards
> through offset 24h."
>
> It would be nice if someone who was involved in this change from 2.1
> to 2.2 would explain why things have changed. It seems to me that
> the net result of this change is to possably invalidate alot of
> existing 2.1 configuration software for no real gain at all. *sigh*
>
> -Richard
>