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Definition of Big Endianness of the PCI Bus

Hi Experts,

First a disclaimer.
I do not intend to start a flame war by writing this mail. I already had one
war on this issue with a colleague from my group.

Now the question I have about big endian operation of PCI bus.

Parden my ignorance but I want to know the exact definition of a big 
endian PCI bus. Nowhere in the PCI specs, I found any direct reference
to byte ordering/endianness etc.
I have searched this topic in the archive. However I could not find it.
( or missed it ?? )
(My question is not directly related to LE to BE or BE to LE conversion.)

>From the documentation of the chipset we are using, it appears to me that 
the definition of normal big endian bus is different from a big endian PCI
We are using GT64120 in our system.

On a normal bus ( CPU bus for e.g. ) the address of a byte lane
depends on the endian mode it is operating in.
For e.g. the byte lane 31:24 would carry byte at offset 0 in BE mode
and byte at offset 3 in LE mode.
If we are transferring 32 bit quantities only, then the data appears the
irrespctive of the endian mode of the bus. 

Does the same rule apply to PCI bus also?

How does a big endian PCI work ?

On a big endian PCI bus, byte lane AD[31:24] would carry byte at offset 
0 in BE mode and it would carry byte at offset 3 in LE mode.
( same as a normal big endian bus )
This is what I was assuming.

the address of the byte lane on a PCI bus is constant irrespective
of the endian mode.
Thus AD[7:0] would carry byte at offset 0 in LE as well as BE.
However in BE mode, this byte would be the MS Byte. In LE mode, that byte
would be the LS Byte.

The documentation for the chipset (we are currently using) indirectly

I could not find something which would support explicitly any one of the
statements. (The chipset I am using seems to be based on the statement #2)

I found one statement on page 9 in PCI 2.2 specifications which is
saying exactly opposite thing to statement #2.

( cut and pasted from PCI specifications )
2.2.2. Address and Data Pins
AD[ 31::00] t/s 
Address and Data are multiplexed on the same PCI pins. A bus transaction 
consists of an address phase followed by one or more data phases. PCI
both read and write bursts. The address phase is the first clock cycle in
which FRAME#
is asserted. During the address phase, AD[ 31::00] contain a physical
address (32 bits). 
For I/O, this is a byte address; for configuration and memory, it is a DWORD
During data phases, AD[ 07::00] contain the least significant byte (lsb) and
AD[ 31::24] 
contain the most significant byte (msb).
Write data is stable and valid when IRDY# is asserted; read data is stable
and valid 
when TRDY# is asserted. Data is transferred during those clocks where both
and TRDY# are asserted.

I have underlined one statement. Does that that statement mean that even 
on a big endian PCI bus, the byte lane 0 ( AD[7:0] ) would carry Least
Significant Byte?

This byte would be at offset 0 in LE mode but it would be at offset 3
in BE mode. (This means the adddress of a byte lane is changing)

This doubt appeared while I was reading a note on mixed endian operation of
Galileo system controller. ( CPU in BE and PCI in LE or vice versa )

Could someone clear my doubt?
Thank you for your time. It was a pretty long mail.
Thanks in advance for any help,


Raghunath Tilak
Amber Networks
Santa Clara