configuration wr & SERR#

["Man Tam" <mtam@mictron.com>]

Hi all:

Is it OK to post (NOT delay transaction) configuration write cycles 01
within
a transparent PCI-PCI bridge?  The only problem that I can see here is
the host @ the primary interface may think that some of the downstream PCI
devices
has been configure properly, however, in reality the bridge is still trying
to configure
the target device @ the secondary interface.  Do u see any other problems?

Second question is related to the useage of "SERR#".  It is commonly used
by the bridge
to report address parity errors @ both primary & secondary interface as
well as OTHER SYSTEM
ERROR where the result will be catastrophic.  First of all, all these three
cases can happen
simultaneously in a bridge enivronment.  How the OS can tell one from the
others?  I know that
for the address parity error, OS can exam the Primary and Secondary Status
register.  How about
OTHER SYSTEM ERROR?  Does it system dependency, there is NO standard way to
report?

Third question is related to the motivation behind asserting SERR# @ the
primary interface whenever
there is an address error @ the secondary interface (i.e. the bridge device
is a target for the transaction
happening @ the secondary interface).  What was the motivation behind it? 
What if the bridge do NOT
assert SERR# in the case, will it cause any compatiability problem in some
system?  Anyway the bridge
may just not claim the cycle at all in the secondary interface.  Basically,
the transaction will be dropped.

Thanks in advance !!!

Man