The PCI bus spec indicates that a Memory read or Memory Write operation with all byte enables inactive is to be treated like a No-Op to the addressed register. We would like to know if anyone is aware of any PCI cards that exhibit side effects from the usage of this option. Potential areas of concern are clearing Read Register status flags (destructive read) or Queue Pointer incrementation when issued a Memory Read with all byte enables inactive.
Likewise for Memory writes, are there any designs that may have side effects if a write with no byte enables active was done to a register (queue register, doorbell). Also, for both Memory Read and Memory Write operations to a PCI card, does anyone not accept the address (raise DEVSEL) if the byte enables are inactive on the first Dword, or terminate the PCI bus transfer when a Dword with no byte enables active is detected.
Thank you in advance for your response.