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Re: PCI-X initialization requirements and FPGAs



Donald Connolly <Donald.Connolly@matrox.com> writes:

> Hello,
> 
> It seems to me that presenting to PCI-X add-in cards the bus segment operation mode and frequency on the rising edge of RST# makes PCI-X device implementations in FPGA quite difficult. FPGAs will start loading their configuration data from a PROM after RST# is deasserted and will be ready to switch to the proper bus mode and frequency only when the configuration download process completes. Adding logic on the board to latch the initialization pattern violates the single load per signal rule. There doesn't seem to be any trivial (or not so trivial) way for a device to detect the bus mode and frequency long after RST# is deasserted.
> 
> FPGA may not be the first technology that comes to mind when designing a 1GB/s interface but these things get faster and bigger every year and they can be valuable devices for ASIC prototyping. Since conventional PCI implementations at 66 MHz are possible in FPGAs today, it should be possible to modify them to work in PCI-X mode easily once PCI-X compliant buffers are made available. It would be a shame to have a standard that precludes the use of FPGAs in PCI-X systems.
> 
> Donald

We are designing a PCI64 board where the PCI interface is handled by a Xilinx Virtex FPGA.
This FPGA family features an 8 bit parallel bus than is used for uploading the bitstream.
This can be clocked at up to 60 MHz, which means than in less than 10 ms the highest
density part (V1000) can be configured. A low density part (like the V300) would take
even less.
I do not know the PCI-X specs in detail, but when I checked the PCI 2.2 requirements
I verified that there should be enough time for RST# to go high to be correctly
latched.

-Arrigo
--
Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	  			phone: (626) 395-3695
Pasadena, CA 91125	  			fax:   (626) 795-8649