Design for Local Side Clock

[Frank Walker <frank_walker@bigfoot.com>]

Thanks everyone for responding to my question about real PCI bus clock
rates.  From the responses, it is pretty clear that the PCI-bus clock
can be expected to vary substantially amongst systems.

This leads me to some questions about local bus clocking.  Many PCI
interface chips (e.g., PLX 9080) provide a buffered PCI clock-out,
ostensibly for use by the local bus.  So, given the fact that the PCI
clock may vary in frequency, is it nonetheless a common design practice
to use such local-bus-side PCI clocks as source for the local bus-side
processor?  Are there any subtle synchronization issues that are
resolved by keeping PCI and local bus clocks phase-locked and/or
identical?  

Tbanks in advance...