Re: DEVSEL# timing in status register

[Richard Walter <rwalter@corp.auspex.com>]

> From Forcone@ILCDDC.COM Wed Nov 17 06:36:33 1999
> 
> The DEVSEL timing was inadvertantly set to MEDIUM instead of SLOW in
> a custom PCI bridge ASIC.
> 
> Can anyone tell me what the consequences of this will be?

Since you are breaking PCI 2.2, Section 6.2, page 192, paragraph 1,
last sentence: ".. and the data returned must indicate the value that
the device is actualy using.", your company will be forever branded as
non-compliant scum of the earth. :)

The DEVSEL timing bits in config space can be used to speed up access
to the subtractive decode agent on a particular PCI bus. (See PCI 2.2,
Section 3.6.1, page 89, paragraphs 3 & 4.)

Essentially:
IF  your device is put onto a PCI bus with a subtractive decode agent
	(99.9% of the time this means it is on the same bus with the
		ISA legacy crud.)
AND there are no other devices that indicate that they are slow decoders
AND the subtractive agent supports variable timing for the subtractive
    decode point
AND software actually changes the subtractive decode point based on
    scanning all active devices

THEN you could have contention when both your device and the subtractive
decode agent device decide at clock 4 that they should claim the cycle
and so both drive DELSEL# active for clock 5.  (Clock #'s reference
Figure 3-17 on page 89 of PCI 2.2)

Realistically, is this a big problem?  Off hand, I'd say probably not,
because the cynical hardware guy in me doubts that software to do the
changing of the subtractive decode point is all that pervasive (if it
exists at all.)  Firmware vendors, do any of your firmwares actually
change the subtractive decode point on subtractive agents?

> Thank You
> Marco

-Richard Walter
rwalter@corp.auspex.com
Note: I speak for myself, not for Auspex.